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Freescale Semiconductor Technical Data
MPC9773 Rev 5, 08/2005
3.3 V 1:12 LVCMOS PLL Clock Generator
The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted for high-performance low-skew clock distribution in mid-range to highperformance networking, computing, and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. Features * * * * * * * * * * * * * * * 1:12 PLL based low-voltage clock generator 3.3 V power supply Internal power-on reset Generates clock signals up to 242.5 MHz Maximum output skew of 250 ps Differential PECL reference clock input Two LVCMOS PLL reference clock inputs External PLL feedback supports zero-delay capability Various feedback and output dividers (refer to Application Section) Supports up to three individual generated output clock frequencies Synchronous output clock stop circuitry for each individual output for power down support Drives up to 24 clock lines Ambient temperature range -40C to +85C Pin and function compatible to the MPC973 52-lead Pb-free package available
MPC9773
3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR
FA SUFFIX 52-LEAD LQFP PACKAGE CASE 848D-03
AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 848D-03
Functional Description The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3. The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition, the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a nonbinary factor. The MPC9773 also supports the 180 phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers, bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the MPC9773. The MPC9773 has an internal power-on reset. The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
All input resistors have a value of 25 k PCLK PCLK VCC CCLK0 CCLK1 CCLK_SEL REF_SEL FB_IN VCO_SEL PLL_EN VCC FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] VCC INV_CLK STOP_DATA STOP_CLK MR/OE 12 Power-On Reset 2 2 2 3 0 1 VCC FB PLL 200-485 MHz 1 0 Ref VCO /2 /1 0 1 0 1 /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 /12, /16, /20 SYNC PULSE
QA0 Bank A CLK Stop QA1 QA2 QA3 QB0 Bank B CLK Stop QB1 QB2 QB3 Bank C CLK Stop 0 1 CLK Stop QC0 QC1 QC2 QC3 QFB CLK Stop QSYNC
Clock Stop
Figure 1. MPC9773 Logic Diagram
GND QB0 VCC QB1 GND QB2 VCC QB3 FB_IN GND QFB VCC FSEL_FB0 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VCC QA2 GND QA1 VCC QA0 GND VCO_SEL 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 MPC9773 20 46 19 47 18 48 17 49 16 50 15 51 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 GND MR/OE STOP_CLK STOP_DATA FSEL_FB2 PLL_EN REF_SEL CCLK_SEL CCLK0 CCLK1 VCC_PLL PCLK PCLK
FSEL_FB1 QSYNC GND QC0 VCC QC1 FSEL_C0 FSEL_C1 QC2 VCC QC3 GND INV_CLK
Figure 2. MPC9773 52-Lead Package Pinout (Top View)
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Table 1. Pin Configuration
Pin CCLK0 CCLK1 PCLK, PCLK FB_IN CCLK_SEL REF_SEL VCO_SEL PLL_EN MR/OE FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] INV_CLK STOP_CLK STOP_DATA QA[0-3] QB[0-3] QC[0-3] QFB QSYNC GND VCC_PLL VCC I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Supply Supply Supply Type LVCMOS LVCMOS LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock Alternative PLL reference clock Differential LVPECL reference clock PLL feedback signal input, connect to an QFB LVCMOS clock reference select LVCMOS/PECL reference clock select VCO operating frequency select PLL enable/PLL bypass mode select Output enable/disable (high-impedance tristate) and device reset Frequency divider select for bank A outputs Frequency divider select for bank B outputs Frequency divider select for bank C outputs Frequency divider select for the QFB output Clock phase selection for outputs QC2 and QC3 Clock input for clock stop circuitry Configuration data input for clock stop circuitry Clock outputs (Bank A) Clock outputs (Bank B) Clock outputs (Bank C) PLL feedback output. Connect to FB_IN. Synchronization pulse output Negative power supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please refer to applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function
Table 2. Function Table (Configuration Controls)
Control REF_SEL CCLK_SEL VCO_SEL PLL_EN Default 1 1 1 1 0 Selects CCLKx as the PLL reference clock Selects CCLK0 Selects VCO / 2. The VCO frequency is scaled by a factor of 2 (low VCO frequency range). 1 Selects the LVPECL inputs as the PLL reference clock Selects CCLK1 Selects VCO / 1 (high VCO frequency range)
Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL internal VCO output. MPC9773 is fully static and no minimum frequency limit enabled. applies. All PLL related AC characteristics are not applicable. QC2 and QC3 are in phase with QC0 and QC1 QC2 and QC3 are inverted (180 phase shift) with respect to QC0 and QC1
INV_CLK MR/OE
1 1
Outputs disabled (high-impedance state) and device is reset. During reset/ Outputs enabled (active) output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9773 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up.
VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency ratios. See Table 3 to Table 6 and the Applications Section for supported frequency ranges and output to input frequency ratios.
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Table 3. Output Divider Bank A (NA)
VCO_SEL 0 0 0 0 1 1 1 1 FSEL_A1 0 0 1 1 0 0 1 1 FSEL_A0 0 1 0 1 0 1 0 1 QA[0:3] VCO / 8 VCO / 12 VCO / 16 VCO / 24 VCO / 4 VCO / 6 VCO / 8 VCO / 12
Table 5. Ouput Divider Bank C (NC)
VCO_SEL 0 0 0 0 1 1 1 1 FSEL_C1 0 0 1 1 0 0 1 1 FSEL_C0 0 1 0 1 0 1 0 1 QC[0:3] VCO / 4 VCO / 8 VCO / 12 VCO / 16 VCO / 2 VCO / 4 VCO / 6 VCO / 8
Table 4. Output Divider Bank B (NB)
VCO_SEL 0 0 0 0 1 1 1 1 FSEL_B1 0 0 1 1 0 0 1 1 FSEL_B0 0 1 0 1 0 1 0 1 QB[0:3] VCO / 8 VCO / 12 VCO / 16 VCO / 20 VCO / 4 VCO / 6 VCO / 8 VCO / 10
Table 6. Output Divider PLL Feedback (M)
VCO_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSEL_FB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QFB VCO / 8 VCO / 12 VCO / 16 VCO / 20 VCO / 16 VCO / 24 VCO / 32 VCO / 40 VCO / 4 VCO / 6 VCO / 8 VCO / 10 VCO / 8 VCO / 12 VCO / 16 VCO / 20
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Table 7. General Specifications
Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 12 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition
Table 8. Absolute Maximum Ratings(1)
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 9. DC Characteristics (VCC = 3.3 V 5%, TA = -40C to 85C)
Symbol VCC_PLL VIH VIL VPP VCMR VOH VOL ZOUT IIN ICC_PLL ICCQ PLL Supply Voltage Input High Voltage Input Low Voltage Peak-to-Peak Input Voltage Common Mode Range(1) PCLK, PCLK PCLK, PCLK 250 1.0 2.4 0.55 0.30 14 - 17 200 8.0 13.5 35 VCC - 0.6 Characteristics Min 3.0 2.0 Typ Max VCC VCC + 0.3 0.8 Unit V V V mV V V V V A mA mA VIN = VCC or GND VCC_PLL Pin All VCC Pins Condition LVCMOS LVCMOS LVCMOS LVPECL LVPECL IOH = -24 mA(2) IOL = 24 mA IOL = 12 mA
Output High Voltage Output Low Voltage Output Impedance Input Current
(3)
Maximum PLL Supply Current Maximum Quiescent Supply Current
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9773 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 3. Inputs have pull-down resistors affecting the input current.
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Table 10. AC Characteristics (VCC = 3.3 V 5%, TA = -40C to 85C)(1), (2)
Symbol fREF Characteristics Input Reference Frequency / 4 feedback / 6 feedback / 8 feedback / 10 feedback / 12 feedback / 16 feedback / 20 feedback / 24 feedback / 32 feedback / 40 feedback Min 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 Typ Max 121.2 80.8 60.6 48.5 40.4 30.3 24.2 20.2 15.1 12.1 250 200 / 2 output / 4 output / 6 output / 8 output / 10 output / 12 output / 16 output / 20 output / 24 output 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 485 242.5 121.2 80.8 60.6 48.5 40.4 30.3 24.2 20.2 20 PCLK, PCLK PCLK, PCLK 400 1.2 2.0 1.0 offset)(6) -3 -4 -166 +3 +4 +166 100 100 100 250 (T/2) -200 0.1 T/2 (T/2) +200 1.0 8.0 8.0 150 100 )(11) / 4 feedback / 6 feedback / 8 feedback / 10 feedback / 12 feedback / 16 feedback / 20 feedback / 24 feedback / 32 feedback / 40 feedback 11 86 13 88 16 19 21 22 27 30 1000 VCC - 0.9 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz mV V ns ns ps ps ps ps ps ps ns ns ns ps ps ps ps ps ps ps ps ps ps ps ps (VCO = 400 MHz) 0.55 to 2.4 V 0.8 to 2.0 V PLL locked LVPECL LVPECL PLL locked Condition PLL locked
PLL bypass
Input Reference Frequency in PLL Bypass Mode fVCO fMAX VCO Frequency Range Output Frequency
fSTOP_CLK VPP VCMR tPW,MIN tR, tF t()
Serial Interface Clock Frequency Peak-to-Peak Input Voltage Common Mode Range(3) Width(4)
Input Reference Pulse
CCLKx Input Rise/Fall Time(5) Propagation Delay (static phase 6.25 MHz < fREF < 65.0 MHz 65.0 MHz < fREF < 125 MHz fREF = 50 MHz and feedback = /8 Output-to-Output Skew(7) within QA outputs within QB outputs within QC outputs all outputs
tSK(O)
DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT()
Output Duty Cycle(8) Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle Jitter(9) Period Jitter(10) I/O Phase Jitter RMS (1
MPC9773 6 Advanced Clock Drivers Device Data Freescale Semiconductor
Table 10. AC Characteristics (VCC = 3.3 V 5%, TA = -40C to 85C)(1), (2)
Symbol BW PLL Closed Loop Characteristics Bandwidth(12) / 4 feedback / 6 feedback / 8 feedback / 10 feedback / 12 feedback / 16 feedback / 20 feedback / 24 feedback / 32 feedback / 40 feedback Min Typ 1.20 - 3.50 0.70 - 2.50 0.50 - 1.80 0.45 - 1.20 0.30 - 1.00 0.25 - 0.70 0.20 - 0.55 0.17 - 0.40 0.12 - 0.30 0.11 - 0.28 10 Max Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ms Condition
tLOCK
Maximum PLL Lock Time
1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The input reference frequency must match the VCO lock range divided by the feedback divider ratio: fREF = fVCO / (M VCO_SEL). 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). 4. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF,MIN. 5. The MPC9773 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. 6. CCLKx or PCLK to FB_IN. Static phase offset depends on the reference frequency. t() [s] = t() [] / (fREF 360). 7. Excluding QSYNC output. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation. 8. Output duty cycle is DC = (0.5 200 ps fOUT) 100%. E.g., the DC range at fOUT = 100 MHz is 48% < DC < 52%. T = output period. 9. Cycle jitter is valid for all outputs in the same divider configuration. 10. Period jitter is valid for all outputs in the same divider configuration. 11. I/O jitter is valid for a VCO frequency of 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter vs. VCO frequency. 12. -3 dB point of PLL transfer characteristics.
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APPLICATIONS INFORMATION
MPC9773 Configurations Configuring the MPC9773 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula:
fOUT = fREF M / N fREF PLL /VCO_SEL /N fOUT
the specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and output divider: fQA[0:3] = fVCO / (VCO_SEL NA) fQB[0:3] = fVCO / (VCO_SEL NB) fQC[0:3] = fVCO / (VCO_SEL NC) Table 11. MPC9773 Divider
/M
Divider M
Function PLL Feedback FSEL_FB[0:3] Bank A Output Divider FSEL_A[0:1] Bank B Output Divider FSEL_B[0:1] Bank C Output Divider FSEL_C[0:1]
VCO_SEL /1 /2 /1 /2 /1 /2 /1 /2
Values 4, 6, 8, 10, 12, 16 8, 12, 16, 20, 24, 32, 40 4, 6, 8, 12 8, 12, 16, 24 4, 6, 8, 10 8, 12, 16, 20 2, 4, 6, 8 4, 8, 12, 16
where fREF is the reference frequency of the selected input clock source (CCLKO, CCLK1 or PCLK), M is the PLL feedback divider and N is an output divider. The PLL feedback divider is configured by the FSEL_FB[2:0] and the output dividers are individually configured for each output bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0] inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 480 MHz in order to achieve stable PLL operation: fVCO,MIN (fREF VCO_SEL M) fVCO,MAX The PLL post-divider VCO_SEL is either a divide-by-one or a divide-by-two and can be used to situate the VCO into
NA NB NC
Table 11 shows the various PLL feedback and output dividers, and Figure 3 and Figure 4 display example configurations for the MPC9773.
fREF = 33.3 MHz
CCLK0 CCLK1 CCLK_SEL 1 VCO_SEL FB_IN 11 00 00 101 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0]
QA[3:0] QB[3:0] QC[3:0] QFB
33.3 MHz 100 MHz 200 MHz
fREF = 25 MHz
CCLK0 CCLK1 CCLK_SEL 1 VCO_SEL FB_IN 00 00 00 011 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0]
QA[3:0] QB[3:0] QC[3:0] QFB
62.5 MHz 62.5 MHz 125 MHz
MPC9773 33.3 MHz (Feedback)
MPC9773 25 MHz (Feedback)
MPC9773 example configuration (feedback of QFB = 33.3 MHz, fVCO = 400 MHz, VCO_SEL = /1, M = 12, NA = 12, NB = 4, NC = 2).
Frequency Range Input QA outputs QB outputs QC outputs Min 16.6 MHz 16.6 MHz 50 MHz 100 MHz Max 40 MHz 40 MHz 120 MHz 240 MHz
MPC9773 example configuration (feedback of QFB = 25 MHz, fVCO = 250 MHz, VCO_SEL = /1, M = 10, NA = 4, NB = 4, NC = 2).
Frequency Range Input QA outputs QB outputs QC outputs Min 20 MHz 50 MHz 50 MHz 100 MHz Max 48 MHz 120 MHz 120 MHz 240 MHz
Figure 3. Example Configuration
Figure 4. Example Configuration
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MPC9773 Individual Output Disable (Clock Stop) Circuitry The individual clock stop (output enable) control of the MPC9773 allows designers, under software control, to implement power management into the clock distribution design. A simple serial interface and a clock stop control logic provides a mechanism through which the MPC9773 clock outputs can be individually stopped in the logic `0' state: The clock stop mechanism allows serial loading of a 12-bit serial input register. This register contains one programmable clock stop bit for 12 of the 14 output clocks. The QC0 and QFB outputs cannot be stopped (disabled) with the serial port. The user can program an output clock to stop (disable) by writing logic `0' to the respective stop enable bit. Likewise, the
user may programmably enable an output clock by writing logic `1' to the respective enable bit. The clock stop logic enables or disables clock outputs during the time when the output would normally be in logic low state, eliminating the possibility of short or `runt' clock pulses. The user can write to the serial input register through the STOP_DATA input by supplying a logic `0' start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC9773 can sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. (See Figure 5.)
STOP_CLK STOP_DATA START QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC
Figure 5. Clock Stop Circuit Programing
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SYNC Output Description The MPC9773 has a system synchronization pulse output QSYNC. In configurations for which the output frequency relationships are not integer multiples of each other, QSYNC provides a signal for system synchronization purposes. The MPC9773 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the
fVCO
coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse is dependent on QA and QC output frequencies: the QSYNC pulse width is equal to the period of the higher of the QA and QC output frequencies. Figure 6 shows various waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank C outputs.
1:1 Mode QA QC QSYNC 2:1 Mode QA QC QSYNC 3:1 Mode QC(/2) QA(/6) QSYNC 3:2 Mode QA(/4) QC(/6) QSYNC 4:1 Mode QC(/2) QA(/8) QSYNC 4:3 Mode QA(/6) QC(/8) QSYNC 6:1 Mode QA(/12) QC(/2) QSYNC
Figure 6. QSYNC Timing Diagram
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Power Supply Filtering The MPC9773 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9773 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA_PLL pin for the MPC9773. Figure 7 illustrates a typical power supply filter scheme. The MPC9773 frequency and phase stability is most susceptible to noise with spectral content in the 100-kHz to 20-MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 8 mA (13.5 mA maximum), assuming that a minimum of 3.0 V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 7 must have a resistance of 5-10 to meet the voltage drop criteria.
RF = 5-10 VCC RF CF 10 nF CF = 22 F VCC_PLL MPC9773 VCC 33...100 nF
Using the MPC9773 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9773. Designs using the MPC9773 as an LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9773 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge, resulting in a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or longterm jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9773 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9773 are connected together, the maximum overall timing uncertainty from the common CCLKx input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consists of 4 components: static phase offset, output skew, feedback board trace delay, and I/O (phase) jitter:
CCLKCommon
-t()
tPD,LINE(FB)
QFBDevice 1
tJIT() +tSK(O) +t()
Figure 7. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7, the filter cut-off frequency is around 4.5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9773 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.
Any QDevice 1
QFBDevice2
tJIT()
Any QDevice 2 Max. skew
+tSK(O) tSK(PP)
Figure 8. MPC9773 Maximum Device-to-Device Skew
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Due to the statistical nature of I/O jitter, an RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12. Table 12. Confidence Factor CF
CF 1 2 3 4 5 6 tjit[] [ps] RMS Probability of Clock Edge within the Distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999
Maximum I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 120 100 80 60 40 20 0 200 250 300 350 400 450 480 VCO frequency [MHz] FB = /12 FB = /6 FB = /24
Figure 10. MPC9773 I/O Jitter
Maximum I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 140 120 tjit[] [ps] RMS 100 80 60 40 20 0 200 FB = /10 FB = /40 FB = /20 250 300 350 400 450 480
The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 9 to Figure 11 to predict a maximum I/O jitter and the specified t() parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation an I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst-case timing uncertainty from the common input reference clock to any output of -455 ps to +455 ps relative to CCLK (PLL feedback = /8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 13 ps RMS max., static phase offset t() = 166 ps): tSK(PP) = [-166ps...166ps] + [-250ps...250ps] + [(13ps -3)...(13ps 3)] + tPD, LINE(FB) tSK(PP) = [-455ps...455ps] + tPD, LINE(FB)
Maximum I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 160 140 120 100 80 60 40 20 0 200
VCO frequency [MHz]
Figure 11. MPC9773 I/O Jitter Driving Transmission Lines The MPC9773 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 , the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high-performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50- resistance to VCC / 2.
FB = /32 FB = /16 FB = /8
tjit[] [ps] RMS
FB =/4 250 300 350 400 VCO frequency [MHz] 450 480
Figure 9. MPC9773 I/O Jitter
MPC9773 12 Advanced Clock Drivers Device Data Freescale Semiconductor
This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9773 clock driver. For the series terminated case, however, there is no DC current draw; thus the outputs can drive multiple series terminated lines. Figure 12 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9773 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC9773 Output Buffer In
14
At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 1. Final skew data pending specification.
3.0 2.5 2.0 OutA tD = 3.8956 OutB tD = 3.9386
RS = 36
ZO = 50 OutA
Voltage (V)
In 1.5 1.0
MPC9773 Output Buffer In
14
RS = 36
ZO = 50 OutB0 ZO = 50 OutB1
0.5 0 2 4 6 8 Time (ns) 10 12 14
RS = 36
Figure 13. Single versus Dual Waveforms Figure 12. Single versus Dual Transmission Lines The waveform plots in Figure 13 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9773 output buffer is more than sufficient to drive 50- transmission lines on the incident edge. Note from the delay measurements in the simulations that a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9773. The output waveform in Figure 13 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36- series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = Z0 = RS = R0 = VL = = VS (Z0 / (RS + R0 + Z0)) 50 || 50 36 || 36 14 3.0 (25 / (18+17+25) 1.31 V Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 14 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched.
MPC9773 Output Buffer
14
RS = 22
ZO = 50
RS = 22
ZO = 50
14 + 22 || 22 = 50 || 50 25 = 25 Figure 14. Optimized Dual Line Termination
MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 13
MPC9773 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 15. CCLK MPC9773 AC Test Reference
Differential Pulse Generator Z = 50
ZO = 50
MPC9773 DUT ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 16. PCLK MPC9773 AC Test Reference
MPC9773 14 Advanced Clock Drivers Device Data Freescale Semiconductor
VCC VCC / 2 GND VCC VCC / 2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device CCLKx VCC VCC / 2 GND FB_IN VCC VCC / 2 GND t()
Figure 17. Output-to-Output Skew tSK(O)
VCC VCC / 2 GND tP T0 DC = tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
Figure 18. Propagation Delay (t(), Static Phase Offset) Test Reference
CCLKx
FB_IN
TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles
Figure 19. Output Duty Cycle (DC)
Figure 20. I/O Jitter
TN
TN+1
TJIT(CC) = |TN-TN+1|
T0
TJIT(PER) = |TN-1/f0|
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
Figure 21. Cycle-to-Cycle Jitter
Figure 22. Period Jitter
VCC = 3.3 V 2.4 0.55 tF tR
Figure 23. Output Transition Time Test Reference
MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 15
PACKAGE DIMENSIONS
CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE
MPC9773 16
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Advanced Clock Drivers Device Data Freescale Semiconductor
PACKAGE DIMENSIONS
CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE
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MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 17
PACKAGE DIMENSIONS
CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE
MPC9773 18
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Advanced Clock Drivers Device Data Freescale Semiconductor
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MPC9773 Rev. 5 08/2005

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